1. Field of the Invention
The present invention relates to semiconductor devices and methods for producing the devices, and particularly relates to a semiconductor device having a contact plug including a polysilicon, and a method for producing the device.
2. Description of the Related Art
Finer semiconductor devices with higher packing density have increasingly been developed in recent years, For example, dynamic random access memory (DRAM) with a high capacity, namely 1 Gbit, has been put into practical use.
Each memory cell in DRAM is basically composed of a gate transistor and a capacitor. One of the diffusion layers included in the gate transistor is connected to a bit line while the other diffusion layer is connected to an electrode of the capacitor.
According to known methods, such components in semiconductor devices are connected with contact plugs formed by filling contact holes with conductive materials. Japanese Unexamined Patent Application Publication No. 2001-024170 discloses a polysilicon contact plug. Japanese Unexamined Patent Application Publication No. 9-074188 discloses a polysilicon plug structure including a heavily doped upper polysilicon layer and a lightly doped lower polysilicon layer. This structure is aimed at inhibiting the diffusion of impurities from the plug portion into diffusion layers of a silicon substrate to suppress junction leakage current in the diffusion layer regions.
The reduction of wiring resistance is becoming essential with the increasing demand for finer semiconductor integrated circuits. In the above DRAM memory cell structure, particularly, polysilicon contact plugs are used to connect one diffusion region of the gate transistor to the bit line and to connect the other diffusion region to the capacitor. A significant subject here is to reduce the contact resistance of the contact plugs.
Sufficiently low contact resistance could previously be attained using polysilicon contact plugs by heat treatment at high temperatures for a long time. Recent devices, however, are difficult to anneal at high temperatures for a long time because the devices require shallow junctions and inhibited impurity diffusion to achieve the transistor performance of the peripheral circuitry.
For example, the annealing of devices with a design rule of 0.11 μm in a furnace is performed at 850° C. or less only for about several minutes. Rapid thermal annealing (RTA) allows heat treatment at higher temperatures, namely 900° C. or more, but only for about tens of seconds.
The resistance of the above wiring is the series resistance of the contact interfaces (interface resistance) and the contact plugs. Two effects can be provided by conventional heat treatment with high heat load at high temperatures for a long time, One is the effect of aggregating oxide films occurring naturally at the interfaces with the substrate into balls to reduce the contact resistance at the interfaces. The other is the effect of allowing the contact plugs to grow larger crystal grains which have fewer crystal grain boundaries. This results in the reduction of the resistance in the plugs.
As described above, however, such heat treatment involving high heat load has become difficult to perform, and the wiring resistance must be reduced under low heat load conditions. The resistance of the contact interfaces was once considered to be the dominant resistance. Studies, however, show that the resistance of the contact interfaces can be reduced by keeping the surface of the semiconductor substrate at the bottom of the contact holes sufficiently clean. The surface of the substrate may be kept clean by, for example, removing etching-damaged layers, such as SiC, formed during the formation of the contact holes, or by controlling the atmosphere in a low-pressure chemical vapor deposition (LP-CVD) apparatus during the introduction of the substrate into the apparatus (reducing the contents of oxygen and moisture to several ppm).
On the other hand, an initial possible approach to reducing the resistance of the contact plugs is solid-phase epitaxial growth at the bottoms of the contact holes on the substrate by depositing and annealing amorphous silicon. This approach, however, cannot meet the low heat load requirements because stable solid-phase epitaxial growth requires hydrogen baking at high temperatures, namely 900° C. or more, for about ten minutes in the same reaction chamber before the deposition of amorphous silicon.
Another possible approach is to increase the concentration of the impurities in the plugs. The resistance decreases with increasing impurity concentration up to a predetermined concentration. Above the predetermined concentration, on the contrary, the resistance increases because the impurities segregate at the crystal grain boundaries. Thus the concentration at which the plug resistance is minimized makes it difficult to further reduce the resistance simply by increasing the concentration.
In addition, an excessively high impurity concentration disadvantageously increases junction leakage current because the impurities in the contact plugs diffuse to the substrate, as shown in Japanese Unexamined Patent Application Publication No. 9-74188. To avoid the problem, according to this publication, the impurity concentration is decreased at the bottom portions of the contact plugs to inhibit the diffusion of the impurities into the substrate.
When, however, this technique is applied to finer contact plugs, the resistance of the plugs by themselves increases. This technique therefore has difficulty in providing low contact resistance in spite of inhibited junction leakage current.